1. Field of the Invention
The present invention relates to a circuit for executing conditional branch instructions on a processor having a pipeline structure widely employed in general purpose computers, minicomputers, microcomputers, digital signal processors, and the like.
2. Description of the Related Art
Instructions executed in processors usually include conditional branch instructions and condition code setting instructions such as logical operation instructions and arithmetical operation instructions. When the condition code setting instruction has been executed, a value of a condition code, which indicates a state of the operation result, such as zero, plus, or minus, is settled, and when the conditional branch instruction is executed, the condition code is examined to determine whether the condition code satisfies a branch condition specified by the instruction, and flow of execution branches to an address specified by the instruction if the branch condition is satisfactory.
In a processor having a pipeline structure constituted by multiple stages, instructions have to be successively fed into a first stage of the pipeline in accordance with order of execution. Nevertheless, after a conditional branch instruction is fed into the first stage, the instruction to be fed next is sometimes not definite because the condition codes for the conditional branch instruction are sometimes not definite at that time because they are settled, or, the conditions for the branch are determined in a latter stage of the pipeline.
Therefore, in a pipeline process, it is important to decide earlier whether or not the branch condition is satisfactory in order to improve the execution rate for instructions including conditional branch instructions.
Japanese Unexamined Patent Publication (Kokai) No. 52-130256 discloses an information processing apparatus comprising a circuit for executing conditional branch instructions in a pipeline process. In this circuit, while a conditional branch instruction flows through the pipeline, it is determined whether a condition code setting instruction not yet settled with a condition code exists at stages later than that of the conditional branch instruction. If such instruction exists, examination of the branch condition for the conditional branch instruction flowing through the pipeline is delayed until all of the condition code setting instructions at latter stages settle the condition codes. After that, if the branch condition is satisfactory, instructions existing at stages earlier than that of the conditional branch instruction are canceled with intermediate results thereof, and an instruction stream at an address specified by the conditional branch instruction is fed into the pipeline. If the branch condition is not satisfactory, feeding of the instruction stream is continued.
In the circuit disclosed in the above publication, determination whether an executed condition code setting instruction exists in latter stages is effected as if all of condition code setting instructions settle the condition codes at the same stage. In fact, some of the instructions such as instructions performing operations between register operands settle the condition codes at a stage earlier than others, but the circuit disclosed in the above publication cannot recognize the earlier settlement of the condition codes.
Japanese Examined Patent Publication (Kokoku) No. 2-13333 discloses an information processing apparatus comprising a circuit for executing conditional branch instructions in a pipeline process, wherein the circuit can recognize earlier settlement of the condition codes. In this circuit, condition code setting instructions fed into the pipeline are separately counted corresponding to respective stages where the instructions settle the condition codes. When condition code setting instructions settle the condition codes at respective stages, the corresponding counts are decremented. When a conditional branch instruction is fed into the first stage, examination of the branch condition is carried out to determine if all of the counts are equal to zero, which indicates that a condition code for the fed conditional branch instruction has been settled. Then, if the settled condition code does not satisfy the branch condition in the examination, an instruction stream at an address next to the address of the conditional branch instruction is fed into the pipeline. If the branch condition is satisfied, an instruction stream at an address specified by the conditional branch instruction is fed.
In the circuit disclosed in the second publication, the earlier settlement of the condition codes can be recognized, but if any of the counts are not equal to zero when a conditional branch instruction is fed into the pipeline, feeding of the instruction stream is interrupted until all of the counts become equal to zero, because the counts are disturbed if any condition code setting instruction is further fed before the condition code for the conditional branch instruction is settled. Therefore, even in the case where the branch condition may not be satisfied, feeding of further instructions is interrupted, and thus, the execution rate is reduced in situations where branch conditions are not satisfied when executing the conditional branch instructions.